Do a chip to carry out the most basic aspects of the design -> flow -> packaging -> test, chip enterprise cost management composition we generally 20% of the cost of human resources, 40% of the flow, 35% of the package, 5% of the test [for China's advanced technology process, the flow of cost control may have been more than 60%].

Test is actually the cheapest part of the chip, in this every company is shouting "reduce costs" in the fierce market, labor costs are rising year by year, foundries and packaging plants in the second side of the market are "Ali Ben Abi Talib", but only Testing seems to be less difficult, "cost reduction" of the bead on the test.

However, if you do the math, you save 50% on testing, only 2.5% on total cost, and 15% on tape or packaging, so testing is free. But testing is the last hurdle to product quality. Without good testing, the product PPM [million failure rate] is so high that returns or compensation are a far cry from the 5% cost.

Chip need to do what test?

Mainly divided into three categories: chip function test,wafer level testing performance test, reliability test, chip product listing test three indispensable links.

Function test to see if the chip is right

Performance test to see if the chip is good

Reliability test to see if the chip is solid

Function test, is to test the system chip parameters, indicators, functions, with people have no words we need to see your October baby born baby is a mule is a horse out for a walk.

Performance testing, because the chip in the production process, there are countless steps that may introduce defects, even if the same batch of wafers and packaging finished product, the chip is also good and bad,failure analysis so the need for screening, people say, is the stone in the egg to pick out the "stone" chip thrown away.

Reliability testing, the chip through the function and performance testing, get a good chip, but this chip will be the most annoying static phenomenon, in the cold, thunderstorms, dog days, snow days can work properly, and whether the chip is able to last for a month, a year, ten years, and so on, all of which are assessed by reliability testing.

Then to realize these tests, what means do we have?

Testing and analyzing methods: board level testing, wafer CP testing, finished product FT testing after packaging, system level SLT testing, reliability for testing, and multiple strategies.

Board-level testing, mainly applied to functional testing, the use of PCB boards + chip to build a "simulation" of the chip's working environment, the chip's interfaces are cited, the detection of the chip's function, or in a variety of harsh environments to see if the chip can work properly. The main equipment to be applied is the instrumentation, and the main thing to be made is the EVB evaluation board.

Wafer CP test, often used in social function analysis test and performance research test, to understand the Chinese chip system function design can be normal, as well as sieve out the chip wafer in the fault handling chip. CP [Chip Probing] as the name suggests is the use of probes [Probe] to tie the chip on the Wafer, all kinds of data signals through the input into the chip, the chip technology output Response to capture and manage comparisons and calculations, there are also some with special scenarios will be used to configure the structure of the adjustment control chip [Trim]. Need for enterprise application of equipment is mainly due to the automatic completion of the test of the main equipment [ATE] + Probe table [Prober] + instrumentation,wafer test we need to make the hardware is the Probe Card [Probe Card].

After the finished product packaging FT test, common function test, performance test and reliability test, check whether the chip function is normal, whether there are defects in the packaging process, but also helps the reliability test to determine whether the chip in the "firestorm" after the normal work. The equipment to be used is mainly Automatic Test Equipment [ ATE ] + Robotic Arm [ Handle ] + Instrumentation. The hardware to be created is Test Board [ Loadboard ] + Test Socket [ Socket ] and so on.

System-level SLT testing is commonly used for functional, performance and reliability testing, often as a supplement to finished product testing. As the name suggests, it is tested in a system environment, that is, the chip is put in its normal working environment to run its function to test its quality. The disadvantage is that it can only cover part of the function, so the coverage is low, so it is usually a supplementary means of FT. The equipment to be applied is mainly a robot, and the hardware to be made is a system board] + test socket.

Reliability testing is mainly on the chip to impose a variety of harsh environments, such as ESD static electricity, that is, simulating the human body or industrial body on the chip to apply instantaneous large voltage. Another example is HTOL (High Temperature Operating Life), which is to accelerate chip aging at high temperatures and then estimate chip life. There is also HAST (Highly Accelerated Stress Test) to test the moisture resistance of the chip package. The product to be tested is placed in harsh temperatures, humidity and pressure, whether the humidity will seep into the package along the interface of the colloid or lead frame, damaging the chip. 

Summarize and Prospect

Chip testing is never a simple egg picker, not only "picky" "rigorous" can be, but also need the whole process of control and participation.

From the beginning of the chip design enterprise, we should consider how to improve the test of students, whether we should add DFT [Design for Test] design, whether we can at the same time through the study of the design of the system function of self-test [FuncBIST] to reduce the dependence on peripheral circuits and test technology and equipment.

When the chip is booted up and verified, the final test vectors should be considered, and the test bench for verification should be written in a cyclic base-based manner so that the generated vectors are easier to convert and avoid data omission.

During the start-up phase, the chip test program should be completed. the development of the ATE test program should be synchronized with the production of the CP/FT hardware to ensure that the chip is debugged on the wafer assembly line, which greatly shortens the development cycle of the chip.

Finally, it is more important to enter the mass production stage, such as how to supervise and control the test yield, how to deal with customer complaints and low PPM, how to continuously optimize the test flow, improve the efficiency of the test program, shorten the test time, reduce the test cost, etc.